   3.3V to 5V low cost Bidirectional converter   The circuit presented is a bidirectional logic signal level converter. It can be used to transfer data between circuits operating at different voltage (e.g. 3.3V and 5V), both serial (SPI, I2C, etc.) and parallel communication, repeating the circuit as many times as there are signals. It works without problems at low frequencies (up to 1MHz), while with increasing operating frequency should be checked the circuit requirements to falling – rising time of pulses.

Author: Dimitrios Porlidas

Curriculum Vitae electronics@porlidas.gr Facebook Linkedin  Its operation is based on the change of the MOS transistor statements as changing the bias. If the output circuit is at high logic state the transistor is in cut-off region and the input circuit is also located at high state due to the pull-up resistor. If the output circuit is at low logic state the transistor is in high conductivity region and transfers the low state at the input circuit. Analytically: Suppose that the circuit operates with low voltage (e.g. 3.3V) is the output circuit and the circuit operates with high voltage (e.g. 5V) is the input circuit. If the output is at logic 1 then Vgs = 0, the transistor is in cut-off region and the input circuit is also located at logic 1 because of the pull-up resistor. If the output is at logic 0 then Vgs = 3.3V, the transistor is in high conductivityregion and the input circuit is at logic 0 too, after the state being transferred through transistor. Assume now that the circuit operates with high voltage (e.g. 5V) is the output circuit and the circuit operates with low voltage (e.g. 3.3V) is the input circuit. If the output is at logic 1 the circuit works the same way as in the previous assumption. If the output is at logic 0 then the transistor becomes in reverse bias. The Drain potential is 0 which is derived from the output of the circuit, while the Source and the Gate have 3.3V by the bias and the pull-up resistor.The transistor is thus in high conductivity region and the input circuit is at logic 0 after the state being transferred through transistor. (Below is an analysis of the specific bias.) In each case the output circuit logic state is transferred to the input circuit at the appropriate voltage level. Analysis of the reverse bias in nMOS. In MOS Drain does not have any structural difference with Source and when it comes to n channel MOS are islets type n in structure (Body) type p. As a result there is a pn junction between the p Body and the n Drain and similarly the Source. In some types of nMOS the Body is connected to a free terminal and if biased at a potential more negative than the source then the VT of the transistors increases, and vice versa. In other types is connected internally to Source and both have a common terminal so VT does not affected. This is the reason that this terminal is used exclusively for Source to those types. pn junction of Body – Drain normally is reversed bias and thus is not conductive. The nMOS used in the specific application is this type. Because of the reverse bias of the transistor when the output circuit is at logic 0, as mentioned above, pn junction Body – Drain is forward biased and therefore conductive. Furthermore the inducted channel is open due to gate bias. We can simulate this connection as if we interchange the Source with the Drain and connect the Body at positive potential. For all these reasons, the transistor is at high conductivity state and the input circuit is at logic 0 after the state being transferred through transistor. Thank you for your support to make my website better. © 2017 Dimitrios Porlidas 